X9CMME Digital Potentiometer Circuit

Xicor’s digitally controlled E²POT ICs provide ergonomic and long-lasting alternatives to mechanical potentiometers. The ICs in the X9CMME series have a 7-bit counter with reversible count direction and a decoder that enables one of the 100 analogue switches.

The outputs of the analogue switches serve as the wiper of a potentiometer, while the inputs are linked to a potential divider composed of 99 equal resistors. The counter state may be stored in a non-volatile EEPROM, so that it can serve as the output value at a subsequent start.

The X9CMM series is designed to operate from 5 V supply lines. The potential across the resistive divider must not exceed 10 V (only 4 V in case of the X9C102). The ON resistance of the analogue switch is about 40 Ohm, so that the current through the wiper is limited to 1 mA.

E²POT ICs have three inputs for the digital drive. The level at U/D determines whether a trailing edge at clock input /INC lowers or raises the counter state. This action only takes place if chip select input /INC is low. A leading edge at CS arranges for the counter state to be stored when /INC is high. When /INC is high, the IC is in the standby mode.

Digital potentiometer circuit diagram

Digital potentiometer schematic

The circuit diagram shows a complete digital potentiometer based on a Type X9CMME. It is provided with two controls, S1 and S2, an optical indicator and a delayed frequency change-over of the clock generator. When keys S1 and S2 are open, resistors R8 and R9 hold the inputs of IC2d, a NAND, as well as the U/D input of IC1 high. The low level at the output of IC2d disables clock generator IC2a. Frequency determining capacitor C1 is discharged in the quiescent state.

When one of the keys is pressed (S1 firmly, S2 gently), the output of IC2d changes state, so that the clock generator and IC1 (via IC2b) are enabled. Capacitor C1 is then charged via R1 and R2 until the input level of IC2a goes low, whereupon the gate output linked to the clock input of IC1 changes state (from low to high). When this happens, C1 is discharged via R1 and D1 until the upper trigger level of IC2a is attained. The gate then changes state again and the above action repeats itself. The clock signal is optically monitored by D3.

When the output of IC2c is high, the gate draws a portion of the charging current from C1, which results in the clock frequency at /INC being relatively low. At the same time that the generator is enabled, C6 begins to be charged gradually via R6 and R7 until IC2c changes states (from high to low). Circuit IC2 then contributes to the charging current to C1, whereupon the clock frequency increases: in the prototype, the frequency rose in four seconds from 1.3 Hz to 3.1 Hz. When the keys are released, the clock generator stops. At the same time, C6 is discharged rapidly via R6 and D2, so that the frequency is low again when the keys are operated anew.
The switch-off delay owing to R4-C2 enables the actual counter state to be stored by the internal logic. The circuit draws a current of 0.3-1.0 mA.

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