Ultra-Low Noise Clock Buffers


Ultra-Low Noise Clock Buffers

Ultra Low Noise Clock Buffers

Texas Instruments Incorporated expanded its high-performance clock buffer portfolio with the introduction of two new universal clock buffer families. The CDCLVC1310 LVCMOS clock buffer delivers an industry-leading phase noise floor of ā€“169 dBc/Hz in crystal mode. The LMK00101/05 complements the family with flexible output voltage level configurations. The LMK00301/04/06/08 differential-ended family offers ultra-low additive jitter of 51 femtoseconds (fs).

In response to today’s communications systems moving to higher data rates that demand stringent system jitter budgets, these devices deliver the lowest jitter, skew, and built-in signal-level translators. These new families support applications like networking and data communications, medical imaging, test and measurement, and radar. Download datasheets and IBIS models, order free samples, or request evaluation modules (EVMs) here: http://www.ti.com/universalbuffers-pr.

CDCLVC1310, LMK00101/05 features and benefits
  • Best-in-class noise floor in crystal mode with ultra-low system additive jitter (25 fs) improves system communications link and signal-to-noise (SNR) performance.
  • Universal input architecture (LVPECL, LVDS, HCSL, SSTL, LVCMOS) and built-in voltage level and signal translator reduce board space by 50 percent.
  • Universal I/O supply voltage (1.5V, 1.8V, 2.5V, 3.3V) simplifies system design and reduces bill of materials (BOM) cost by 50 percent.
LMK0030x (LMK00301/04/06/08) features and benefits
  • Additive jitter of 51 fs RMS at 156.25 MHz (12 kHz ā€“ 20 MHz) improves system link performance with double the flexibility of the nearest competitive device.
  • Universal output architecture with built-in voltage level and signal translators eliminate the need for interface logic and external components, reducing board space by half.
  • Ability to configure output clocks reduces customers’ R&D device evaluation cost by more than 50 percent.
TI offers a large portfolio of complementary devices to optimize the high-speed signal chain. Some of the devices complementing these clock buffers are:
  • Clock generators such as the LMK03806 and CDCM61001.
  • High-speed data converters such as the DAC3484, ADS4149 and ADC12D1800RF families.
  • Power management ICs such as the TPS54120.
  • Digital signal processors (DSPs) such as the TMS320C66x.
Availability and pricing

The below universal clock buffers are in full production now and available from TI and authorized distributors. Also listed are the pin and package sizes, with suggested resale prices in quantities of 1,000 units.

In 2Q12 TI will release another fan-out buffer for low-power requirements capable of distributing eight copies of the differential-ended clock outputs.

Learn more about TI’s clock buffer solutions:
  • Order free samples, request EVMs, and download datasheets and IBIS models: http://www.ti.com/universalbuffers-pr.
  • See the entire clock and timing portfolio at http://www.ti.com/clock-pr.
  • Ask questions and help solve problems with fellow engineers in the Clocks & Timers Forum at the TI E2Eā„¢ Community.
  • Quickly search TI’s entire interface portfolio or download the latest selection guide: http://www.ti.com/interface-pr.
  • To read technical articles about clock buffers or other signal chain and power topics, visit: http://www.ti.com/aaj-pr.

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