ON Semiconductor Timing Considerations with the Dual-CAN Transceiver


This application note from ON SEMICONDUCTOR is prepared by Pavel Drazdil. This application note has shown with examples of different bus topologies, that the introduction of an AMIS?42700 dual?CAN transceiver has an important influence on the timing considerations in the full CAN?bus system. Although favorable from many other points of view explained in the section “Introductory and Scope” – flexible CAN topology, increased fault?tolerance and improved signal integrity through long lines ? the presence of a dual?CAN transceiver in general narrows down the timing criteria resulting from the CAN. As a practical consequence, it is not possible to achieve the maximum high?speed CAN bit rate (1 Mbps, see the results in Table 4) if the communication messages are supposed to pass via the dual?CAN component. This can be bypassed either by decreasing the communication speed or by implementing additional application?specific measures in the protocol or the topology itself (e.g. ensuring that only some combinations of nodes can enter into arbitration or acknowledgement process, and placing these nodes on the same bus branches). These interventions would be, however, difficult to accept as they would require special hardware and/or software implementations compared to the fully standard CAN bus systems.

ON Semiconductor Timing Considerations with the Dual CAN Transceiver

ON Semiconductor Timing Considerations with the Dual-CAN Transceiver

Application note’s content including the introduction and scope, AMIS-42700 Block diagram, symbols and notation, timing characteristics, the simplified functional symbol and a signal-flow diagram. repeater/dual-CAN configuration, and more.

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