Mapping Defects on Integrated Circuits
Creating a system to localize failure mechanisms causing abnormal electrical behavior, including those linked to complex parameters (such as frequencies, amplitudes, and digital values contained in registers), in integrated circuits (ICs).
Improving a conventional faults mapping system using NI PXI hardware and the NI LabVIEW FPGA Module.
Fault localization is complex due to decreased individual pattern sizes, increased metallization levels, and decreased voltage supplies. We needed to localize a defect measuring less than a few micrometers in a component of several square millimeters. There are several ways to do this, including using global fault isolation methods.
One method uses a laser to scan an IC surface while measuring current or voltage variations induced by the laser’s photoelectric or thermal effects. With the thermal laser (λ≈1.3 m), the beam locally heats the component to change its electrical behavior. An analog system monitors some parameters (currents or voltages) during scanning. Dedicated software running on a PC then creates a map representing the circuit’s heat sensitivity. Faults are generally localized by comparing the map obtained for a reference circuit with the one resulting from a faulty circuit. We used a Hamamatsu Phemos 1000 that can create maps with 1,024 × 1,024 pixel resolution.
Conventional Method Limitations
With the standard Optical Beam Induced Resistive-Change (OBIRCH) laser thermal stimulation method, we can only measure voltage or current changes under local heating. We extended this method by mapping complex variables such as frequencies, amplitudes, and digital values stored in registers.
Hardware System Setup
We developed and validated our solution by analyzing a failure in a component that manages cell phone energy (battery power and voltage regulation) and conversions (audio, radio frequency, and supervision).
This circuit contains an A/D converter (ADC) to measure various currents and voltages during phone operation. On failing components, conversion results shifted several bits (least significant).
We used an NI PXI-1036 chassis equipped with an NI PXI-8102 controller and an NI PXI-7852R field-programmable gate array (FPGA) module. This NI system is inserted between the device interface board and the fault isolation equipment (Phemos 1000).
This assembly ensures the component startup and the ADC control. It initiates conversions and collects the results via serial peripheral interface (SPI) bus. It performs scale conversion and transmits data to the fault localization equipment.
The laser scans the chip in 72 seconds to build an image made of 1024 × 1024 pixels. Each point must be acquired and processed in less than 65 μs (pixel clock period).
We chosed NI hardware because it fully met our requirements. The NI products are low cost, fast enough to process each pixel in less than 65 μs, and programmable with the LabVIEW FPGA Module.
Software System Setup
We created an autonomous system without requiring expertise in complex programming languages. We used LabVIEW FPGA to program the system because it provides the developer with all the needed layers: drivers, APIs, function libraries, graphical interfaces, compilation and synthesis chains.
We downloaded and customized a free SPI controller from IPNet. This block can communicate with various SPI peripherals. We simplified it by removing unnecessary options and created a cell optimized for our needs.
We initiated A/D conversions into the FPGA algorithm, retrieved the results, performed a scaling, and exported data to the Fault Isolation Equipment (Hamamatsu Phemos 1000).
During the mapping construction, the Phemos 1000 is autonomous; it controls the scanning laser, makes voltage and current measurements, and builds laser excitation sensitivity maps. An external signal can be monitored by using an analog input of the equipment. We connected one of the analog PXI-7852R module outputs on this input.
The Phemos 1000 and PXI chassis can operate asynchronously or synchronously. We validated both methods. The asynchronous method is simple to implement, but the pixel processing must be less than 65 μs. The synchronous mode is more complex and has a longer processing time. In our tests, processing was fast enough to use the asynchronous mode.
We used the previous development to the conversion results of a reference unit and a failing one. The two circuits had significantly different results. The laser strongly altered the ADC behavior when scanning two capacitors on the defective part. Simulations showed that a 100 fA leakage of the identified elements explained the electrical fault. Thus, with the method we developed, we could identify two defects: a silicon manufacturing process defect generating an abnormal leakage in some capacitors, and a component design weakness where the converter architecture was too sensitive to a very low leak rate. We made changes at the application level to correct this problem.
The solution we created using NI PXI and LabVIEW FPGA is economical. We developed it without the help of programmable logic circuit experts. It greatly increases the possibility of classical faults isolation methods, giving capability to analyze complex parameters such as frequencies, amplitudes, and digital values contained in registers. With the FPGA, we mapped heat-sensitive areas on an IC in just a few minutes. It would take many hours with a production tester system.
We used this solution to localize a defect in an ADC. The obtained mappings were pointing to internal capacitors. These components had a 100 fA leak, which produced a shift in conversion results. We confirmed this mechanism failure using simulations, and corrected the problem at the application level.
We can now use this system in the ST-Ericsson quality laboratory for all failure-analysis cases involving complex quantities and adapted to thermal laser stimulation.