Low Cost FPGA with 6 Gbps SERDES
The new LatticeECP4 family is the fourth generation of innovative, low cost, low power FPGAs with hard-wired Intellectual Property Communication Engines and powerful DSP Blocks. The innovative LatticeECP4 FPGA family is ideal for cost- and power-sensitive wireline, wireless, video, industrial, and computing applications. The new LatticeECP4 FPGA family offers versatile 6G SERDES for high speed data transmission, built-in MACO Communication Engines for efficient protocol processing, 7x more powerful DSP Blocks for wireless and video, 1066 Mbps DDR3 memory interfaces, high density on-chip memory and up to 250K logic elements (LUTs).
High Performance Innovations
High Quality 6G SERDES
The LatticeECP4 FPGAs contain up to 16 CEI-Compliant 6 Gbps SERDES channels in both low cost wire-bonded and high performance flip chip packages, giving customers the choice to deploy the LatticeECP4 FPGA in chip to chip as well as long reach backplane applications. The SERDES channels can be operated at speeds from 155 Mbps to 6 Gbps and have been qualified for a number of wireline, wireless, and system design protocols – 10 Gigabit Ethernet, 1 Gigabit Ethernet, SGMII, XAUI, RXAUI, PCI Express 2.1, SRIO 2.0, and CPRI. Please visit the LatticeECP4 low power SERDES page for more information.
10X More Efficient MACO Communication Engines
The powerful MACO Communication Engines are hard-wired Intellectual Property (IP) blocks that implement popular communication protocols using only 10% of the silicon resources and power compared to similar implementations in other FPGA fabrics. MACO stands for ‘Multiple Access Cost Optimized,’ as these Engines can be accessed from 6G SERDES or High Speed I/Os. The LatticeECP4 Communication Engines portfolio includes solutions for PCI Express 2.1, multiple 10 Gigabit Ethernet MACs and Tri-speed Ethernet MACs, as well as Serial Rapid I/O (SRIO) 2.1. LatticeECP4 FPGAs incorporate the industry’s highest density hard IP blocks for efficient communication. The LatticeECP4 FPGAs can incorporate up to 22 Communication Engines, whereas competitive “mid-range” FPGAs have only PCI Express and/or a few Ethernet MAC IP blocks. Please visit the LatticeECP4 MACO Communication Engines page for more information.
7X More Powerful DSP Blocks
The LatticeECP4 family features powerful digital signal processing (Power sysDSP) blocks with innovations that offer 7x the performance of competitive FPGAs. These innovations enable customers to implement complex, multi-antenna wireless systems (4×4 MIMO 40 MHz) and high performance video processing algorithms in low cost, low power FPGA platforms. The fully featured LatticeECP4 DSP Blocks include 18×18 multipliers, ALUs, wide adder-trees and carry chains for cascadability. Moreover, up to 576 multiplers can be cascaded together to build complex filters. Please visit the LatticeECP4 DSP technology page for more information about the powerful LatticeECP4 FPGAs.
High Speed I/Os with Embedded CDRs
The LatticeECP4 FPGAs have 50% faster differential system I/Os (GIGA sysIOs) compared to the previous generation LatticeECP3 family. The GIGA sysIOs run at speeds up to 1.25 Gbps. With embedded clock data recovery (CDR) circuits, GIGA sysIOs can be used to implement numerous serial Gigabit Ethernet and SGMII interfaces. The GIGA sysIO CDRs conserve 6G SERDES for other high speed applications. The low cost, high performance 1066 Mbps DDR3 memory interface reduces system cost. Please visit the LatticeECP4 high speed I/O page to learn more about the broad range available.
- Low Cost, Low Power FPGA Fabric
- Low power 65nm process with 4-input look-up table (LUT) fabric
- Logic densities from 30K to 250K LUTs
- Up to 10.6 Mbits of Embedded Block RAMs (EBRs)
- Up to 600 Kbits of Distributed RAM
- High Speed Embedded SERDES
- CEI-Compliant 6G SERDES in low-cost packages
- Up to 16 channels with data rates from 155 Mbps to 6 Gbps
- Lower power consumption of 175mW per channel at 6 Gbps
- Buit-in pre-empahsis and decision feedback equalization (DFE)
- MACO Communication Engines
- Up to 22 hard-wired IP Engines for popular protocols
- PCIe 2.1 ×4, 10GbE, Tri-speed MAC, SRIO 2.1
- Seamless interfaces with SERDES/PCS and fabric
- Flexible System Planner Software Design Tool
- Powerful DSP Blocks (Power sysDSP)
- Fully featured DSP Blocks with multiply, accumulate, addition, and subtraction
- Up to 576 cascadable 18×18 multipliers with ALUs and wide adder trees
- Unique booster and pre-adder logic increases throughput 4X
- Build complex filters for Wireless and Video applications
- High Speed I/O
- Differential I/Os up to 1.25 Gbps data rate (GIGA sysIOs)
- Gigabit Serial I/Os using embedded CDRs (Clock Data Recovery Circuits)
- Up to 40 embedded CDRs
- 1066 Mbps DDR3 memory interface
- Flexible sysIO Buffers
- LVCMOS 33/25/18/15/12 & PCI
- SSTL 33/25/18/15 & HSTL15 & HSTL18
- LVDS, Bus-LVDS, RSDS, MLVDS & LVPECL
- Voltage Level Shifters
- sysCLOCK PLL and DLL
- 8 DLLs and 8 PLLs per device
- Wide Range of Package and User I/O Options
- Up to 512 user I/O pins
- 6G short reach (SR) interfaces on low cost wire-bond fpBGA packages
- 6G long reach (LR) interfaces on high performance flip-chip fcBGA packages
- Pb-free and RoHS compliant
- Advanced Configuration Options
- Configure with SPI boot Flash or parallel burst-mode Flash
- Dual-boot provides backup configuration copy
- 128-bit AES encryption
- Live updates with TransFR Technology
The next generation LatticeECP4 FPGAs with high-speed data interfaces, premium Communication Engines and powerful DSP Blocks have been optimized for a wide range of wireline and wireless communication and video processing applications. The unique capabilities of LatticeECP4 FPGAs for these applications are discussed below:
The LatticeECP4 FPGAs have a number of unique features to help customers design multimode Remote Radio Heads (RRH) and 4G base stations. The 7x more powerful DSP Blocks facilitate linearization of signals from multiple antennas. The LatticeECP4 is the only FPGA that offers low-latency variation CPRI and SRIO 2.1 interfaces for wireless applications. The SRIO 2.1 interface is implemented in the efficient MACO Communication Engine.
The large portfolio of MACO Communication Engines, high quality SERDES and GIGA sysIOs with embedded CDR circuits make the LatticeECP4 an ideal platform for building state of the art Wireless Backhaul, Wireline Access, Switches & Routers, and Storage & Computing systems. The LatticeECP4 FPGAs have up to 40 embedded CDR circuits, which can be used to implement Gigabit Ethernet and SGMII interfaces using numerous GIGA sysIO pins. The GIGA sysIOs with embedded CDRs and 6G SERDES/PCS can be used to build high port density communication platforms.
The LatticeECP4 FPGAs have an optimum combination of resources for mainstream video transmission, codecs, analytics, and processing applications. The low jitter 6G SERDES and built-in MACO Communication Engines allow high-fidelity capture of video data and transmission over long distances. The powerful DSP Blocks lead to cost-efficient implementation of complex video processing algorithms. The high-speed DDR3 memory interface and differential I/O interface enable simultaneous processing of multiple video channels. These building blocks in LatticeECP4 FPGAs enable customers to quickly design Industrial Video Cameras, Surveillance Cameras, Broadcast, Display, Medical Imaging, and Automotive Entertainment systems.