Limiting Cross-Conduction Current in Synchronous Buck Converter Designs


The following application note is an article from Alan Elbanhawy, taken from the Fairchild Semiconductor’s website (fairchildsemi.com). The application will explore several solutions that consider inductances involved in this design to better understand this complex phenomenon, demonstrate how the gate inductance tends to make the cross conduction current or shoot through worse, emonstrate how source inductance helps to keep the gate source voltage at a lower level, and present the equations that describe the gate voltage in time as a function of all the circuit parameters.

The synchronous buck converter is the topology of choice for PC and notebook computers. The reason for this favored status is that this topology offers designers an ease of control, a small footprint and high power conversion efficiencies at a relatively low cost. An important consideration in designing this synchronous buck converter is limiting the shoot-through or cross conduction current. Through mathematical analysis, MOSFET designers and power supplydesigners test the suitability of a specific device for its use as a synchronous rectifier in the converter. — Quote

This is the complete equivalent circuit diagram including inter-electrode ESR :

Limiting Cross Conduction Current in Synchronous Buck Converter Designs
Find more details about the article from the FAIRCHILD SEMICONDUCTOR by downloading the pdf document from the following source:

LIMITING CROSS CONDUCTION BUCK CONVERTER DESIGN DOWNLOAD


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