High-Speed Optical Ethernet Testing
BEAVERTON, Ore., Feb 27, 2012 – Tektronix, Inc., the world’s leading manufacturer of oscilloscopes, today announced a comprehensive optical compliance testing toolset for the DSA8300 Digital Signal Analyzer sampling oscilloscope. The new toolset provides a single mainframe solution for optical compliance test for Ethernet at speeds ≥10G, 40G, and 100G (4×25) with up to 4 times the throughput, superior native jitter, and an integrated clock recovery solution. This complete solution eliminates the need for additional test equipment such as optical-to-electric converters. In addition, it features an updated jitter analysis toolset offering the industry’s only bounded uncorrelated jitter (BUJ) separation techniques for better identification of crosstalk issues.
The DSA8300 Digital Serial Analyzer is a versatile modular architecture, providing exceptional bandwidth and signal fidelity, the highest-performance TDR and interconnect analysis, the most accurate analysis of signal impairments for current and emerging data communications technologies. With 6 module slots, the DSA8300 can simultaneously accommodate a clock recovery instrument, a precision phase reference module, and multiple electric and optical acquisition modules for a broad range of test configurations in one instrument. The DSA8300 Series is a complete toolset for Optical engineering teams. With all of the capability in one instrument, engineers improve lab bench space, reduce calibration expense and interact with a familiar user interface.
“Engineers want a single test instrument for critical optical measurements,” said Brian Reich, general manager, Performance Oscilloscopes, Tektronix. “This instrument set covers test support for all of the critical IEEE802.3 and Fibre Channel standards. And by providing the industry’s first sampling oscilloscope solution with BUJ analysis, we are helping to address crosstalk test challenges faced by our customers on these higher data rates.”
The latest version of the IEEE Ethernet Optical and Electrical standards at 40 and 100 Gb/s are 4 lane and 10 lane architectures. Given the multi-lane architecture, a critical design challenge is to accurately identify lane-adjacent crosstalk, which typically shows up as BUJ. Until now, traditional jitter separation techniques like Dual-Dirac have not accounted for non-periodic part of BUJ (NPBUJ) and instead erroneously added it to random jitter, leading to inaccurate jitter estimates compared to results for a Bit Error Ratio Tester (BERT). The new NPBUJ capability for the DSA8300 is unique in the industry and addresses new decomposition requirements to ensure that crosstalk signal issues are measured and accounted for properly and accurately.