High-Speed FPGA 100G Interfaces


High-Speed FPGA 100G Interfaces

High Speed FPGA 100G Interfaces

Xilinx, Inc. announced the industry’s first dual 100 Gbps Gearbox solution for connecting 100G interfaces with the newest generation of high-density, 100 Gbps CFP2 optical modules. Incorporating a single 28nm Virtex®-7 HT FPGA and Xilinx Gearbox intellectual property (IP) cores, the solution overcomes the initial hurdles of leveraging the new CFP2 optics supporting 100GE, OTU4 and 10× 10 MSA specifications. This allows higher density 100G line cards and transmission equipment while lowering overall system power consumption and solution cost through integration. By offering the implementation based on the Virtex-7 HT FPGA family with 28 Gbps transceivers, Xilinx can provide communications customers with twice the density and more advanced debugging features compared to competing devices as well as replace what would be a three chip ASSP design.

The global demand fueled by the surge in multimedia content and the rise of cloud computing is creating an unquenchable thirst for more bandwidth. This in turn is driving the need for adoption of more high-speed 100G interfaces with higher port densities in the optical and packet networking equipment across the network – core, aggregation, data center and transmission. The move toward increased numbers of 100G interfaces per line card in the core and aggregation nodes has become critical to achieve scale, network simplicity and an overall cost reduction in running and managing networks. CFP2 optical modules that are half the size of CFP modules with significantly lower power consumption require an external 100G gearbox to achieve density gains and power advantages based on their form factor. Further gains are achieved when both the CFP2 modules and the gearbox conform to 100GE, OTU4 and 10× 10 MSA specifications, which require using 4× 25G and 10× 10G serial links schemes for systems side interfaces. A single IP core for connecting multiple 100G interfaces into a single chip takes integration to the next level. Combining the Xilinx Dual 100G Gearbox with other OTN or packet processing functionality in a single chip provides an unprecedented level of integration, while reducing overall systems power and lowering the total BOM costs by up to forty percent.

“The anticipated pace of growth in the 100G market provides an unprecedented opportunity in the optical transmission space for FPGA vendors to secure a domineering role in providing chips for a far-reaching period of time,” said Mark Lutkowitz, Principal of Telecom Pragmatics. “Xilinx’s Gearbox IP will be a key enabler in meeting the higher density and lower power demands for second-generation CFPs.”

The Xilinx Dual 100G Gearbox solution includes the Gearbox IP cores for dual 100 Gbps channels supporting two CFP2 and future CFP4 optical modules and the Virtex-7 HT FPGA silicon (7VH290T, 7VH580T or 7VH870T). The solution maps data between the ten and four serial lane interfaces, in both ingress and egress directions. It converts data streams of either CAUI (10× 10.3125G) or OTL4.10 (10× 11.18G) to four lanes of proposed CAUI4 (4× 25.78G) or OTL4.4 (4× 27.95G). In the case of 100GE, the original twenty PCS lanes are reconstructed internally, allowing per-lane debug, skew insertion, and data manipulation, all under user control. In addition, the Xilinx Dual 100G Gearbox solution integrates advanced debugging capabilities to replicate basic test equipment thereby delivering development cost savings. Unique in the FPGA industry is the dedicated transceivers in the Virtex-7 HT Dual Gearbox devices that are pinned out to connect seamlessly with CFP2 optics without additional vias for crossovers to improve signal integrity.

Xilinx’s Dual 100G Gearbox implementation enables customers to convert existing CFP-based line cards to CFP2 so they can take advantage of higher density, lower power and lower cost per line card. This conversion can happen quickly without any changes to the CAUI-based FPGA/ASIC/NPU portion of the card.

“This new Xilinx offering of Dual 100 Gbps Gearbox IP cores and Virtex 7-HT FPGA silicon enables equipment vendors to connect their 100 Gbps interfaces with up to two CFP2 optical modules while lowering the overall BOM by reducing chip count and allowing integration with OTN framers as well as 100G bridges into a single chip,” said Gilles Garcia, Director of Wired Communications at Xilinx. “Additionally, the programmability of the Virtex-7 HT FPGA ensures that the equipment vendors can easily stay abreast of the changes in standards that are still evolving in the optical, Ethernet and OTN market space.”

Along with lowering the power consumption and accelerating product development cycles through advanced debug functionality, integration of additional functions such as multiple 100GE MAC, 100G OTN framers and transponders/muxponders or 120G muxsar, 200G MAC to Interlaken bridges in the same Virtex-7 HT FPGA lowers total line card and system BOM for applications in data center and OTN switches, POT-S, switches and routers that are challenged on cost and power.

By simplifying the interface to optical modules, more functions are being integrated into the devices, thereby minimizing the power density. Designers can now have 200G of throughput (Xilinx Dual 100G Gearbox) for less than 10W of power. Further by reducing the number of chips the Virtex-7 HT FPGA Dual 100G Gearbox solution provides, an interface to CFP2 optical modules. The only other option for customers to use is two single port ASSP chips to connect to two 100G channels, for a gearbox implementation and a third chip for the OTN framer or 100GE MAC, which increases BOM, power and design complexity.

For more information on Xilinx’s Dual 100G Gearbox, please download the 100G Dual Gearbox: Improving Port Density on Line Cards in Core Network Equipment white paper on Xilinx.com.

Industry Standards

There are three standards bodies presently engaged in defining the standards associated with 100 Gbps transmission: the Institute of Electrical & Electronics Engineers (IEEE), the International Telecommunication Union (ITU) and the Optical Internetworking Forum (OIF); and two multi service agreements (MSA) engaged in defining specifications for 100G optical modules: CFP MSA and 10 × 10 MSA . With the standards still under evolution, the programmability of FPGAs insulates customers from changes being made in these proposed standards. The mix of transceiver configurations offered in the Virtex-7 HT FPGA family allows both interfacing modes currently being discussed to be easily addressed during updates and upon approval.

Xilinx Virtex-7 HT FPGA Family Overview

Xilinx Virtex-7 HT FPGAs with integrated transceivers deliver the industry’s highest bandwidth platform. The Virtex-7 HT family offers the largest single-FPGA solution for 100 Gbps – 400 Gbps line cards for the next generation communication systems by delivering a total of 2.8 Tbps full duplex serial bandwidth. Virtex-7 HT devices support up to seventy-two 10G-KR backplane-compliant 13.1 Gbps transceivers for line and client side interfaces and up to sixteen high performance transceivers to interface with the next generation CFP2 optical modules.


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