Unlike BJTs, thermal runaway does not occur with FETs, as already discussed in our blog. However, the wide differences in maximum and minimum **transfer characteristics** make I_{D} levels unpredictable with simple fixed-gate bias voltage. To obtain reasonable limits on quiescent drain currents I_{D} and drain-source voltage V_{DS}, source resistor and potential divider bias techniques must be used. With few exceptions, MOSFET bias circuits are similar to those used for **JFET**s. Various FET biasing circuits are discussed below:

**Fixed Bias.**

Fixed bias-FET

DC bias of a FET device needs setting of gate-source voltage V_{GS} to give desired drain current I_{D} . For a JFET drain current is limited by the saturation current I_{DS}. Since the FET has such a high input impedance that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed battery voltage is not affected or loaded by the FET.

Fixed dc bias isobtained using a battery V_{QG}. This battery ensures that the gate is always negative with respect to source and no current flows through resistor R_{G} and gate terminal that isI_{G} =0. The battery provides a voltage V_{GS} to bias the N-channel JFET, but no resultingcurrent is drawn from the battery V_{GG}. Resistor R_{G} is included to allow any ac signal applied through capacitor C to develop across R_{G}. While any ac signal will develop across R_{G}, the dc voltage drop across R_{G} is equal to I_{G} R_{G } *i.e. *0 volt.

The gate-source voltage V_{GS} is then

V_{GS}** = **– v_{G} – v_{s} = – v_{GG} – 0 = – V_{GG}

The drain -source current I_{D}is then fixed by the gate-source voltage as determined by equation.

This current then causes a voltage drop across the drain resistor R_{D} and is given asV_{RD} = I_{D}R_{Dand output voltage, Vout = VDD – IDRD}

**Self-Bias.**

FET-Self Bias circuit

This is the most common method for biasing a JFET. Self-bias circuit for N-channel JFET is shown in figure.

Since no gate current flows through the reverse-biased gate-source, the gate current I_{G} = 0 and, therefore,v_{G} = i_{G} R_{G} = 0

With a drain current I_{D} the voltage at the S is

V_{s}= I_{D}R_{s}

The gate-source voltage is then

V_{Gs}= V_{G }– V_{s} = 0 – I_{D} R_{s} = – I_{D} R_{s}

So voltage drop across resistance R_{s} provides thebiasing voltage V_{Gg} and no external source is requiredfor biasing and this is the reason that it is called self-biasing.

The operating point *(*that is zero signal I_{D} and V_{DS}) can easily be determined from equationand equation given below :

V_{DS = }V_{DD} – I_{D}** (**R_{D + }R_{S})

Thus dc conditions of JFET amplifier are fully specified.Self biasing of a JFET stabilizes its quiescent operating point against any change in its parameters like transconductance. Let the given JFET be replaced by another JFET having the double conductance then drain current will also try to be double but since any increase in voltage drop across R_{s}, therefore, gate-source voltage, V_{GS} becomes more negative and thus increase in drain current is reduced.

**Potential-Divider Biasing.**

fet-potential-divider-biasing

A slightly modified form of dc bias is provided by thecircuit shown in figure. The resistors R_{Gl }and R_{G2} form a potential divider across drain supply V_{DD}. The voltage V_{2} across R_{G2} provides the necessary bias. The additional gate resistor R_{Gl} from gate to supply voltage facilitates in larger adjustment of the dc bias point and permits use of larger valued R_{S}.

The gate is reverse biased so that I_{G} = 0 and gate voltage

V_{G }=V_{2 }=(V_{DD}/R_{ G1 + }R_{ G2 }) *R_{G2}

And

V_{GS}** = **v_{G} – v_{s }= V_{G }– I_{D} R_{s}

_{ The circuit is so designed that ID Rs is greater than VG so that VGS is negative. This provides correct bias voltage.}

The operating point can be determined as

I_{D} = (V_{2} – V_{GS})/ R_{S}

And

V_{DS} = V_{DD} Ã¢Â€Â“ I_{D} (R_{D} + R_{S})