The circuit in the
diagram enables a negative voltage to be derived without the use of
integrated circuits. Instead, it uses five n-p-n transistors that are
driven by a 1 kHz (approx) TTL clock. When the clock input is high, transistors T1 and T2 link capacitor C1 to the supply voltage, UIN,
which typically is 5 V. During this process, transistor T5 conducts so
that T3 and T4 are off. When the clock input is low, T5 is cut off,
whereupon transistors T3 and T4 are switched on via pull-up resistor R6
and either R4 or R5.
This results in the charge on C1 being shared between this capacitor
and C2 Since the +ve terminal of C2 is at ground potential, its –ve
terminal must become negative w.r.t. earth. The high level at the clock
input must be of the same order as the positive input voltage, UIN,
otherwise T1 cannot be switched on. The clock frequency should be
around 1 kHz to ensure a duty cycle ratio of 1:1. Altering the ratio
results in a different level of negative output voltage, but this is
always smaller than that with a ratio of 1:1.